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Disambiguation of "Arima, Eishi"

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Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches.

, , , , , , and . ICCD, page 149-156. IEEE Computer Society, (2015)

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Other publications of authors with the same name

Evaluation of Power Management Control on the Supercomputer Fugaku., , , and . CLUSTER, page 484-493. IEEE, (2020)Probabilistic Job History Conversion and Performance Model Generation for Malleable Scheduling Simulations., , , , and . ISC Workshops, volume 13999 of Lecture Notes in Computer Science, page 82-94. Springer, (2023)Power/Performance/Area Evaluations for Next-Generation HPC Processors using the A64FX Chip., , , , and . COOL CHIPS, page 1-6. IEEE, (2021)Pattern-Aware Staging for Hybrid Memory Systems., and . ISC, volume 12151 of Lecture Notes in Computer Science, page 474-495. Springer, (2020)GreenCourier: Carbon-Aware Scheduling for Serverless Functions., , , , , and . WOSC@Middleware, page 18-23. ACM, (2023)D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory., , , , , , , , and . DATE, page 1813-1818. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Orchestrated Co-scheduling, Resource Partitioning, and Power Capping on CPU-GPU Heterogeneous Systems via Machine Learning., , , and . ARCS, volume 13642 of Lecture Notes in Computer Science, page 51-67. Springer, (2022)Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches., , , , , , and . ICCD, page 149-156. IEEE Computer Society, (2015)Classification-Based Unified Cache Replacement via Partitioned Victim Address History.. DSD, page 101-108. IEEE, (2020)On the Convergence of Malleability and the HPC PowerStack: Exploiting Dynamism in Over-Provisioned and Power-Constrained HPC Systems., , and . ISC Workshops, volume 13387 of Lecture Notes in Computer Science, page 206-217. Springer, (2022)