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Disambiguation of "Pomeranz, Irith"

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On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios.

, , , , , and . VLSI Design, page 59-64. IEEE Computer Society, (2005)

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Irith Baumann

Irith Wiegand

Irith Bittmann

Alexander Pomeranz

Irith Bittmann

 

Other publications of authors with the same name

Multicycle Tests With Fault Detection Test Data for Improved Logic Diagnosis.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (5): 1587-1591 (2022)Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 4862-4872 (2022)Maximal Independent Fault Set for Gate-Exhaustive Faults.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (3): 598-602 (2021)Storage-Based Logic Built-in Self-Test With Multicycle Tests.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (10): 3553-3557 (2022)Vector-restoration-based static compaction using random initial omission., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (11): 1587-1592 (2004)Storage-Based Logic Built-In Self-Test with Variable-Length Test Data.. DFT, page 1-6. IEEE, (2022)Input Test Data Volume Reduction Using Seed Complementation and Multiple LFSRs.. VTS, page 1-6. IEEE, (2020)Functional Broadside Tests with Minimum and Maximum Switching Activity., and . J. Low Power Electron., 4 (3): 429-437 (2008)Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits., and . IEEE Trans. Dependable Secur. Comput., 6 (3): 231-240 (2009)Worst-case and average-case analysis of n-detection test sets and test generation strategies., and . IET Comput. Digit. Tech., 1 (4): 353-363 (2007)