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Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators., , , , , , , , , and 3 other author(s). CoRR, (2023)3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis., , , , and . ICCD, page 254-259. IEEE Computer Society, (2009)Interface engineering of Si1-xGex gate stacks for high performance dual channel CMOS., , , , , , , , , and 1 other author(s). ASICON, page 573-576. IEEE, (2017)PBTI in InGaAs MOS capacitors with Al2O3/HfO2/TiN gate stacks: Interface-state generation., , , , and . IRPS, page 5. IEEE, (2018)In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory., , , , , , , , , and 8 other author(s). CoRR, (2022)Gradient descent-based programming of analog in-memory computing cores., , , , , , , , , and 4 other author(s). CoRR, (2023)Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited)., , , , , , , , , and 11 other author(s). IRPS, page 1-10. IEEE, (2023)Impact of Phase-Change Memory Flicker Noise and Weight Drift on Analog Hardware Inference for Large-Scale Deep Learning Networks., , , , , , , , , and 4 other author(s). Adv. Intell. Syst., (2022)Hardware and Software Co-optimization for the Initialization Failure of the ReRAM-based Cross-bar Array., , , , and . ACM J. Emerg. Technol. Comput. Syst., 16 (4): 36:1-36:19 (2020)Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation., , , , , , , , , and 21 other author(s). IRPS, page 1-6. IEEE, (2021)