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Exploring Fault-Tolerant Network-on-Chip Architectures.

D. Park, C. Nicopoulos, J. Kim, N. Vijaykrishnan, and C. Das. DSN, page 93-104. IEEE Computer Society, (2006)

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P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

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GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility.Y. Chen, M. Lee, G. Dai, M. Zhou, N. Challapalle, T. Wang, Y. Yu, Y. Liu, Y. Wang, H. Yang and 2 other author(s). IEEE Trans. Emerg. Top. Comput., 12 (1): 84-96 (January 2024)Robust Coreset Construction for Distributed Machine Learning.H. Lu, M. Li, T. He, S. Wang, V. Narayanan, and K. Chan. IEEE J. Sel. Areas Commun., 38 (10): 2400-2417 (2020)Leakage Energy Management in Cache Hierarchies.L. Li, I. Kadayif, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. Irwin, and A. Sivasubramaniam. IEEE PACT, page 131-140. IEEE Computer Society, (2002)Fine-to-Coarse Object Classification of Very Large Images.Z. Hakimi, and V. Narayanan. ICIP, page 3498-3502. IEEE, (2023)Experimental Evaluation of Energy Behavior of Iteration Space Tiling.M. Kandemir, N. Vijaykrishnan, M. Irwin, and H. Kim. LCPC, volume 2017 of Lecture Notes in Computer Science, page 142-157. Springer, (2000)A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications.U. Heo, X. Li, H. Liu, S. Gupta, S. Datta, and V. Narayanan. VLSID, page 304-309. IEEE Computer Society, (2015)NEBULA: A Neuromorphic Spin-Based Ultra-Low Power Architecture for SNNs and ANNs.S. Singh, A. Sarma, N. Jao, A. Pattnaik, S. Lu, K. Yang, A. Sengupta, V. Narayanan, and C. Das. ISCA, page 363-376. IEEE, (2020)Cryogenic In-Memory Matrix-Vector Multiplication using Ferroelectric Superconducting Quantum Interference Device (FE-SQUID).S. Alam, J. Hutchins, M. Hossain, K. Ni, V. Narayanan, and A. Aziz. DAC, page 1-6. IEEE, (2023)Analyzing Soft Errors in Leakage Optimized SRAM Design.V. Degalahal, N. Vijaykrishnan, and M. Irwin. VLSI Design, page 227-233. IEEE Computer Society, (2003)Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors.V. Saripalli, V. Narayanan, and S. Datta. VLSI Design, page 399-404. IEEE Computer Society, (2010)

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Disambiguation of "Vijaykrishnan, Narayanan"

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Exploring Fault-Tolerant Network-on-Chip Architectures.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Vijaykrishnan, Narayanan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Exploring Fault-Tolerant Network-on-Chip Architectures.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
Harvard
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Exploring Fault-Tolerant Network-on-Chip Architectures.