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Disambiguation of "Mantovani, Paolo"

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Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration.

, , and . ICS, page 27:1-27:12. ACM, (2016)

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Mauro Mantovani

Dario Mantovani

Giordano Paolo

Nadine Didier-Mantovani

Paolo Molteni

 

Other publications of authors with the same name

High-level synthesis of accelerators in embedded scalable platforms., , and . ASP-DAC, page 204-211. IEEE, (2016)Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study., , and . ACM Great Lakes Symposium on VLSI, page 163-168. ACM, (2011)Opinion: Why science needs philosophy, , , , , , , , and . Proceedings of the National Academy of Sciences, 116 (10): 3948--3952 (2019)A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components., , , , , , , , , and 8 other author(s). ICCAD, page 20:1-20:9. ACM, (2022)Agile SoC Development with Open ESP : Invited Paper., , , , , , , , and . ICCAD, page 96:1-96:9. IEEE, (2020)Accelerators and Coherence: An SoC Perspective., , and . IEEE Micro, 38 (6): 36-45 (2018)On the design of scalable and reusable accelerators for big data applications., , , , and . Conf. Computing Frontiers, page 406-411. ACM, (2016)A synchronous latency-insensitive RISC for better than worst-case design., and . Integr., (2015)A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC., , , , , , , , , and 8 other author(s). ESSCIRC, page 269-272. IEEE, (2022)Runtime reconfigurable memory hierarchy in embedded scalable platforms., , and . ASP-DAC, page 719-726. ACM, (2019)