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A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.

T. Jia, P. Mantovani, M. dos Santos, D. Giri, J. Zuckerman, E. Loscalzo, M. Cochet, K. Swaminathan, G. Tombesi, J. Zhang, N. Chandramoorthy, J. Wellman, K. Tien, L. Carloni, K. Shepard, D. Brooks, G. Wei, and P. Bose. ESSCIRC, page 269-272. IEEE, (2022)

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Jia Jia

Tianyu Zhao

Tianyu Chen

Tianyu Wu

Other publications of authors with the same name

An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture.T. Jia, Y. Wei, R. Joseph, and J. Gu. IEEE J. Solid State Circuits, 55 (8): 2259-2269 (2020)A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique.T. Jia, Y. Ju, and J. Gu. IEEE J. Solid State Circuits, 56 (1): 55-65 (2021)Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration.G. Zacharopoulos, A. Ejjeh, Y. Jing, E. Yang, T. Jia, I. Brumar, J. Intan, M. Huzaifa, S. Adve, V. Adve and 2 other author(s). CoRR, (2022)(Invited) Software-guided greybox design methodology with integrated power and clock management.T. Jia, Y. Fan, R. Joseph, and J. Gu. MWSCAS, page 894-897. IEEE, (2017)Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration.G. Zacharopoulos, A. Ejjeh, Y. Jing, E. Yang, T. Jia, I. Brumar, J. Intan, M. Huzaifa, S. Adve, V. Adve and 2 other author(s). ACM Trans. Embed. Comput. Syst., 22 (3): 53:1-53:23 (2023)OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge.T. Jia, E. Yang, Y. Hsiao, J. Cruz, D. Brooks, G. Wei, and V. Reddi. DATE, page 909-914. IEEE, (2022)FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference.E. Yang, T. Jia, D. Brooks, and G. Wei. ASAP, page 266-273. IEEE, (2021)A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.T. Jia, P. Mantovani, M. dos Santos, D. Giri, J. Zuckerman, E. Loscalzo, M. Cochet, K. Swaminathan, G. Tombesi, J. Zhang and 8 other author(s). ESSCIRC, page 269-272. IEEE, (2022)Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems.Z. Wan, A. Anwar, Y. Hsiao, T. Jia, V. Reddi, and A. Raychowdhury. DAC, page 841-846. IEEE, (2021)A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware.Y. Dong, T. Jia, K. Du, Y. Jing, Q. Wang, P. Zhan, Y. Zhang, F. Yan, Y. Ma, Y. Liang and 2 other author(s). DAC, page 1-6. IEEE, (2023)

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Disambiguation of "Jia, Tianyu"

Please choose a person to relate this publication to

Jia Jia

Tianyu Zhao

Tianyu Chen

Tianyu Chen

Tianyu Wu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Jia, Tianyu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.

Please choose a person to relate this publication to

Jia Jia

Tianyu Zhao

Tianyu Chen

Tianyu Chen

Tianyu Wu

Other publications of authors with the same name

Disambiguation