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Disambiguation of "Kishida, Ryo"

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Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation.

, , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 104-A (2): 516-524 (2021)

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Ryo Sugihara

Ryo Kohsaka

Jong Won Ryoo

So Young Ryou

Mun Il Ryoo

 

Other publications of authors with the same name

Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 104-A (2): 516-524 (2021)Investigation of Hybrid ADC Combined with First-order Feedforward Incremental and SAR ADCs., , , and . ISPACS, page 1-2. IEEE, (2019)Bias Temperature Instability Depending on Body Bias through Buried Oxide (BOX) Layer in a 65 nm Fully-Depleted Silicon-On-Insulator Process., , and . IRPS, page 1-6. IEEE, (2021)Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement., , , , and . IOLTS, page 305-309. IEEE, (2019)Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement., , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2020)Duty Ratio and Capacitance Analysis of AC/DC Converter without Current Control Circuit., , , and . ISPACS, page 1-2. IEEE, (2019)Examination of Incremental ADC with SAR ADC to Reduce Conversion Time with High Accuracy., , , and . ISPACS, page 1-2. IEEE, (2019)Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (12): 2758-2763 (2017)An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process., , and . IRPS, page 4-1. IEEE, (2022)A Novel C-2αC Ladder Based Non-binary DAC for SAR-ADC Using Unit Capacitors., , , and . ISPACS, page 457-462. IEEE, (2018)