( en | de | ru )

 

Disambiguation of "Huda, Safeen"

Author of the publication

copydeleteadd this publication to your clipboard
A Full-stack Accelerator Search Technique for Vision Applications.

, , , , , and . CoRR, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Huda Kaufmann

Egbert Huda

Huda Kanaah

Armin Huda

Christiane Huda

 

Other publications of authors with the same name

Towards PVT-Tolerant Glitch-Free Operation in FPGAs., and . FPGA, page 90-99. ACM, (2016)A full-stack search technique for domain optimized deep learning accelerators., , , , , , and . ASPLOS, page 27-42. ACM, (2022)Resiliency at Scale: Managing Google's TPUv4 Machine Learning Supercomputer., , , , , , , , , and 5 other author(s). NSDI, page 761-774. USENIX Association, (2024)Hybrid LUT/Multiplexer FPGA Logic Architectures., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (4): 1280-1292 (2016)A Full-stack Accelerator Search Technique for Vision Applications., , , , , and . CoRR, (2021)Learning to Design Accurate Deep Learning Accelerators with Inaccurate Multipliers., , , , , and . DATE, page 184-189. IEEE, (2022)A Novel STT-MRAM Cell With Disturbance-Free Read Operation., and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (6): 1534-1547 (2013)Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS., , , , , , and . ISSCC, page 256-257. IEEE, (2010)Charge recycling for power reduction in FPGA interconnect., , and . FPL, page 1-8. IEEE, (2013)Optimizing effective interconnect capacitance for FPGA power reduction., , and . FPGA, page 11-20. ACM, (2014)