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Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes.

, and . IEEE Trans. Computers, 25 (9): 945-949 (1976)

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Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment., , and . DAC, page 414-419. ACM Press, (1995)On a Class of Fault-Tolerant Multiprocessor Network Architectures.. ICDCS, page 302-311. IEEE Computer Society, (1982)A Fault Tolerant Hybrid Memory Structure and Memory Management Algorithms., and . IEEE Trans. Computers, 44 (3): 408-418 (1995)Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off., and . IEEE Trans. Computers, 46 (3): 372-378 (1997)The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI., and . IEEE Trans. Computers, 38 (4): 567-581 (1989)Correction: IEEE Transactions on Computers 41(1): 122-123 (1991).Design and Analysis of a Gracefully Degrading Interleaved Memory System., , , and . IEEE Trans. Computers, 39 (1): 63-71 (1990)Modeling Live and Dead Lines in Cache Memory Systems., , and . IEEE Trans. Computers, 42 (1): 1-14 (1993)The Effect of Program Behavior on Fault Observability., and . IEEE Trans. Computers, 45 (8): 868-880 (1996)Store Address Generator with On-Line Fault-Detection Capability., , and . IEEE Trans. Computers, 26 (11): 1144-1151 (1977)Soft Error Mitigation in Switch Modules of SRAM-based FPGAs., , , and . ISCAS, page 141-144. IEEE, (2007)