( en | de | ru )

 

Disambiguation of "Mutoh, Shin'ichiro"

Author of the publication

copydeleteadd this publication to your clipboard
Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield.

, , , , , , , and . IET Circuits Devices Syst., 6 (4): 260-270 (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Shin'ichiro Nakamura

 

Other publications of authors with the same name

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (10): 2301-2314 (2012)Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation., , , , and . IEICE Electron. Express, 7 (9): 640-646 (2010)A 1-V high-speed MTCMOS circuit scheme for power-down application circuits., , , , and . IEEE J. Solid State Circuits, 32 (6): 861-869 (1997)Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications., , , , , , , and . ISSCC, page 504-505. IEEE, (2010)Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield., , , , , , , and . IET Circuits Devices Syst., 6 (4): 260-270 (2012)Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (4): 230-234 (2011)1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS., , , , , and . IEEE J. Solid State Circuits, 30 (8): 847-854 (August 1995)A 2-Mb/s, UHF-band, wireless sensor node for real-time multi-point sensing., , , , , and . ISCAS (4), page 912-915. IEEE, (2004)A 1-V Cyclic A/D Converter Using FD-SOI Sample/Hold Circuits for Sensor Networks., , , and . IEICE Trans. Electron., 88-C (4): 479-483 (2005)Design and Performance of a Sub-Nano-Ampere Two-Stage Power Management Circuit in 0.35-µm CMOS for Dust-Size Sensor Nodes., , , and . IEICE Trans. Electron., 94-C (7): 1206-1211 (2011)