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A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.

X. Zhu, Y. Chen, M. Kibune, Y. Tomita, T. Hamada, H. Tamura, S. Tsukamoto, and T. Kuroda. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2456-2462 (2010)

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Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

Other publications of authors with the same name

Optimizing effective interconnect capacitance for FPGA power reduction.S. Huda, J. Anderson, and H. Tamura. FPGA, page 11-20. ACM, (2014)Jitter injection for on-chip jitter measurement in PI-based CDRs.J. Liang, A. Sheikholeslami, H. Tamura, and H. Yamaguchi. CICC, page 1-4. IEEE, (2017)A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE.C. Ting, M. Jalali, A. Sheikholeslami, M. Kibune, and H. Tamura. CICC, page 1-4. IEEE, (2014)An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection.M. Jalali, R. Shivnaraine, A. Sheikholeslami, M. Kibune, and H. Tamura. CICC, page 1-8. IEEE, (2013)A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process.Y. Doi, S. Masaki, T. Chiba, H. Higashi, H. Yamaguchi, H. Takauchi, H. Ishida, K. Gotoh, J. Ogawa, and H. Tamura. CICC, page 131-134. IEEE, (2005)Charge recycling for power reduction in FPGA interconnect.S. Huda, J. Anderson, and H. Tamura. FPL, page 1-8. IEEE, (2013)A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.X. Zhu, Y. Chen, M. Kibune, Y. Tomita, T. Hamada, H. Tamura, S. Tsukamoto, and T. Kuroda. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2456-2462 (2010)Replica Exchange MCMC Hardware With Automatic Temperature Selection and Parallel Trial.K. Dabiri, M. Malekmohammadi, A. Sheikholeslami, and H. Tamura. IEEE Trans. Parallel Distributed Syst., 31 (7): 1681-1692 (2020)Efficient correlation-based discretization of continuous variables for annealing machines.Y. Furue, M. Konoshima, H. Tamura, and J. Ohkubo. CoRR, (2023)Generating gradients in the energy landscape using rectified linear type cost functions for efficiently solving 0/1 matrix factorization in Simulated Annealing.M. Konoshima, H. Tamura, and Y. Kabashima. CoRR, (2023)

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Disambiguation of "Tamura, Hirotaka"

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A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.

Please choose a person to relate this publication to

Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tamura, Hirotaka"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.

Please choose a person to relate this publication to

Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.