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Disambiguation of "Raychowdhury, Arijit"

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A 55nm 50nJ/encode 13nJ/decode Homomorphic Encryption Crypto-Engine for IoT Nodes to Enable Secure Computation on Encrypted Data.

, , , and . CICC, page 1-4. IEEE, (2019)

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Arijit Ghosh

Arijit Kundu

Arijit Maitra

Arijit Biswas

Arijit Mukherjee

 

Other publications of authors with the same name

Efficient Signal Reconstruction via Distributed Least Square Optimization on a Systolic FPGA Architecture., , , , and . ICASSP, page 1493-1497. IEEE, (2019)A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware training., and . A-SSCC, page 309-312. IEEE, (2017)Learning to Walk: Spike Based Reinforcement Learning for Hexapod Robot Central Pattern Generation., , , and . AICAS, page 208-212. IEEE, (2020)XBAROPT - Enabling Ultra-Pipelined, Novel STT MRAM Based Processing-in-Memory DNN Accelerator., , , and . AICAS, page 36-40. IEEE, (2020)Energy-Recovery Techniques to Reduce On-Chip Power Density in Molecular Nanotechnologies., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (8): 1580-1589 (2005)OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers., , , and . IEEE J. Solid State Circuits, 55 (3): 629-638 (2020)A Survey of FPGA-Based Robotic Computing., , , , , , , and . CoRR, (2020)MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles., , , , , , , and . CoRR, (2021)Online Reward-Based Training of Spiking Central Pattern Generator for Hexapod Locomotion., , , and . VLSI-SOC, page 208-209. IEEE, (2020)Towards CIM-friendly and Energy-Efficient DNN Accelerator via Bit-level Sparsity., and . VLSI-SoC, page 1-2. IEEE, (2022)