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Aggressive Dynamic Execution of Decoded Traces., , , and . VLSI Signal Processing, 22 (1): 65-75 (1999)A digit online arithmetic simulator., and . ICPP, page 304-306. IEEE Computer Society, (1982)Using Memory Compression for Energy Reduction in an Embedded Java System., , , , and . Journal of Circuits, Systems, and Computers, 11 (5): 537-556 (2002)Accurate Estimation of Combinational Circuit Activity., , , and . DAC, page 618-622. ACM Press, (1995)Validation of an Architectural Level Power Analysis Technique., , , and . DAC, page 242-245. ACM Press, (1998)Exploring performance-power tradeoffs in providing reliability for NoC-based MPSoCs., , and . ISQED, page 495-501. IEEE, (2011)Managing Leakage Energy in Cache Hierarchies., , , , , , and . J. Instruction-Level Parallelism, (2003)Steven P. Levitan (1950-2016)., and . IEEE Des. Test, 33 (3): 142-143 (2016)Design considerations for databus charge recovery., , , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (1): 104-106 (2001)A clock power model to evaluate impact of architectural and technology optimizations., , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (6): 844-855 (2002)