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Disambiguation of "Raghavan, Praveen"

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Parallelization exploration of wireless applications using MPA.

, , , , , , , and . PARCO, volume 19 of Advances in Parallel Computing, page 712-719. IOS Press, (2009)

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Raghavan Vallur

Praveen Konidala

Paurush Praveen

Sarada Raghavan

Raghavan Chinnadurai

 

Other publications of authors with the same name

Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors., , , , , and . J. Signal Process. Syst., 64 (1): 75-92 (2011)Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor., , , , and . VLSI Design, page 201-207. IEEE Computer Society, (2008)The defect-centric perspective of device and circuit reliability - From individual defects to circuits., , , , , , , , , and 5 other author(s). ESSDERC, page 218-225. IEEE, (2015)CMOS low-power transceivers for 60GHz multi Gbit/s communications., , , , , , , , , and 7 other author(s). CICC, page 1-8. IEEE, (2013)Novel energy-efficient scalable soft-output SSFE MIMO detector architectures., , , , , and . ICSAMOS, page 165-171. IEEE, (2009)Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy., , , , , , , , , and 3 other author(s). ISSCC, page 568-569. IEEE, (2007)An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating., , , , , and . DSD, page 693-700. IEEE Computer Society, (2011)Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors., , , , , and . ISCAS, page 121-124. IEEE, (2007)System-level assessment and area evaluation of Spin Wave logic circuits., , , , , , , and . NANOARCH, page 25-30. IEEE Computer Society/ACM, (2014)How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?, , , , and . ICCAD, page 87. ACM, (2016)