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Disambiguation of "Waidyasooriya, Hasitha Muthumala"

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Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors.

, , , and . IEEE Trans. Circuits Syst. Video Techn., 21 (10): 1453-1466 (2011)

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Karunasiri Muthumala

 

Other publications of authors with the same name

Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++., , and . MWSCAS, page 1-4. IEEE, (2022)Benchmarks for FPGA-Targeted High-Level-Synthesis., , and . CANDAR, page 232-238. IEEE, (2019)Hardware-oriented succinct-data-structure based on block-size-constrained compression., , and . SoCPaR, page 136-140. IEEE, (2015)Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays., , and . ERSA, page 291-294. CSREA Press, (2009)FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators., , , and . ISCAS, page 1339-1342. IEEE, (2012)Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time., , , and . ERSA, page 281-284. CSREA Press, (2010)Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores., , and . ERSA, page 179-186. CSREA Press, (2010)Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation., , , , , and . IEICE Trans. Electron., 95-C (12): 1872-1882 (2012)FPGA-Based Prototype of a Quantum Annealing Simulator for Sparse Ising Model., , and . MCSoC, page 195-199. IEEE, (2022)OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions., , , and . Int. J. Reconfigurable Comput., (2017)