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Disambiguation of "Arimoto, Kazutami"

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3D2 processing architecture - High reliability and low power computing for novel nano tactile sensor array.

, , , , , and . ISOCC, page 199-200. IEEE, (2016)

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Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation., , , , , , and . SoCC, page 519-524. IEEE, (2010)A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test., , , , , , , and . IEICE Trans. Electron., 92-C (4): 453-459 (2009)Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters., , , , , , and . IEEE Des. Test Comput., 10 (2): 6-12 (1993)Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor., , , , , , , , and . IEICE Trans. Inf. Syst., 90-D (8): 1312-1315 (2007)Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer., , , , , , , , and . IEICE Trans. Inf. Syst., 90-D (1): 334-345 (2007)An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller., , , , , , , , , and 1 other author(s). COOL Chips, page 1-3. IEEE Computer Society, (2011)Design methodology of embedded DRAM with virtual-socket architecture., , , , , , , and . IEEE J. Solid State Circuits, 36 (1): 46-54 (2001)A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 40 (1): 204-212 (2005)A Low Power Embedded DRAM Macro for Battery-Operated LSIs., , , , , , , , , and 2 other author(s). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 2991-3000 (2003)PEARL: Power-Aware, Dependable, and High-Performance Communication Link Using PCI Express., , , , and . GreenCom/CPSCom, page 284-291. IEEE Computer Society, (2010)