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An Automated Compiler for RISC-V Based DNN Accelerator.

Z. Wu, W. Xie, X. Yi, H. Yang, R. Pu, X. Xiong, H. Yao, C. Chen, J. Tao, and F. Yang. ISCAS, page 3097-3101. IEEE, (2022)

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Xianjun Xiong

Xiong Qi

Guangwei Xiong

Lixiang Xiong

Ning Xiong

Other publications of authors with the same name

NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models.X. Yi, J. Yu, Z. Wu, X. Xiong, D. Xu, C. Chen, J. Tao, and F. Yang. ISCAS, page 2806-2810. IEEE, (2022)TPNoC: An Efficient Topology Reconfigurable NoC Generator.J. Yu, F. Yang, X. Yi, C. Chen, J. Tao, D. Xu, X. Xiong, and H. Yang. ACM Great Lakes Symposium on VLSI, page 77-82. ACM, (2023)FullSparse: A Sparse-Aware GEMM Accelerator with Online Sparsity Prediction.J. Yu, Y. Fan, H. Wang, Y. Qiao, Z. Wu, X. Xiong, X. Yao, H. Yao, and Y. Zhang. CF, ACM, (2024)SFFTNet: Sparse Feature Fusion Transformer Network for Image Deblurring.F. Lei, C. Liu, W. Li, M. e Jing, X. Xiong, X. Zhu, and Y. Fan. ISCAS, page 1-5. IEEE, (2024)ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test.H. Zhang, H. Zhu, S. He, M. Li, C. Wang, X. Xiong, H. Tian, X. Zeng, and C. Chen. DATE, page 1-6. IEEE, (2024)A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight.Y. Lin, Y. Wang, X. Hu, J. Feng, G. Wen, X. Xiong, H. Tian, and Y. Xie. ASICON, page 1-4. IEEE, (2021)A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization.X. Jia, H. Zhu, Y. Wang, J. Zhang, F. Lin, X. Xiong, D. Xu, C. Chen, and Q. Liu. ISCAS, page 2816-2820. IEEE, (2022)LauWS: Local Adaptive Unstructured Weight Sparsity of Load Balance for DNN in Near-Data Processing.Z. Li, W. Wang, X. Zhong, M. Li, J. Yang, Y. Lin, G. Kim, Y. Song, C. Wang, and X. Xiong. ISCAS, page 1-5. IEEE, (2024)A Design of 16TOPS Efficient GEMM Module in Deep Learning Accelerator.G. Lu, D. Xu, N. Wang, X. Zhang, D. Zhen, H. Lei, Y. Bai, D. Kong, H. Ruan, Z. Chi and 2 other author(s). ICTA, page 59-60. IEEE, (2020)An Automated Compiler for RISC-V Based DNN Accelerator.Z. Wu, W. Xie, X. Yi, H. Yang, R. Pu, X. Xiong, H. Yao, C. Chen, J. Tao, and F. Yang. ISCAS, page 3097-3101. IEEE, (2022)

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Disambiguation of "Xiong, Xiankui"

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An Automated Compiler for RISC-V Based DNN Accelerator.

Please choose a person to relate this publication to

Xianjun Xiong

Xiong Qi

Guangwei Xiong

Lixiang Xiong

Ning Xiong

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Xiong, Xiankui"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An Automated Compiler for RISC-V Based DNN Accelerator.

Please choose a person to relate this publication to

Xianjun Xiong

Xiong Qi

Guangwei Xiong

Lixiang Xiong

Ning Xiong

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An Automated Compiler for RISC-V Based DNN Accelerator.