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Disambiguation of "Masselos, Kostas"

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A reusable IP FFT core for DSP applications.

, , , , , , and . ISCAS (3), page 621-624. IEEE, (2004)

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Kostas Buraselis

Kostas Michaelides

Kostas Papamantellos

Kostas Semites

Kostas Kanauka

 

Other publications of authors with the same name

Execution time comparison of lifting-based 2D wavelet transforms implementations on a VLIW DSP., , and . ISCAS, IEEE, (2006)Strategy for power-efficient design of parallel systems., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 7 (2): 258-265 (1999)A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints., , , , , and . VLSI Signal Processing, 26 (3): 291-317 (2000)Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations., , , , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 1027-1036. Springer, (2002)A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints., , , , and . ISLPED, page 270-272. ACM, (1999)Power efficient data path synthesis of sum-of-products computations., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (3): 446-450 (2003)A novel algorithm for low-power image and video coding., , , and . IEEE Trans. Circuits Syst. Video Techn., 8 (3): 258-263 (1998)System-Level Modeling of Dynamically Reconfigurable Co-processors., , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 881-885. Springer, (2004)XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation., , and . ISVLSI, page 375-380. IEEE Computer Society, (2010)Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures., , , , and . ICECS, page 285-288. IEEE, (2001)