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Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications., , , , , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 540-549. Springer, (2004)Design and simulation of a nanoelectronic single-electron universal Control-Control-Not gate., , and . Microelectron. J., 35 (5): 471-478 (2004)Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors., , , , , , and . J. VLSI Signal Process., 44 (1-2): 153-171 (2006)Power, performance and area exploration of block matching algorithms mapped on programmable processors., , , , , , , and . ICIP (3), page 728-731. IEEE, (2001)Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications., , , , , , and . DATE, page 740-745. European Design and Automation Association, Leuven, Belgium, (2006)Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique., , and . VLSI-SoC, page 204-209. IEEE, (2006)A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck., , , , , and . DATE, page 946-947. IEEE Computer Society, (2005)Improving the Memory Bandwidth Utilization Using Loop Transformations., , , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 117-126. Springer, (2005)Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms., , , , , and . Real Time Imaging, 9 (6): 371-386 (2003)A novel methodology for designing high-performance and low-energy FPGA routing architecture., , , and . FPGA, page 224. ACM, (2006)