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Fast and accurate BER estimation methodology for I/O links based on extreme value theory.

, , , , , , and . DATE, page 503-508. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 52 (12): 3458-3473 (2017)A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 53 (4): 1227-1237 (2018)Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors., , , and . Microelectron. J., (2016)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET., , , , , , , , , and 2 other author(s). ESSCIRC, page 183-186. IEEE, (2017)A flexible DSP block to enhance FPGA arithmetic performance., , , , , and . FPT, page 70-77. IEEE Computer Society, (2009)Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs., , , and . VLSI-SoC, page 149-154. IEEE, (2010)A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 53 (4): 1214-1226 (2018)A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions., , , , , , , and . CHES, volume 5747 of Lecture Notes in Computer Science, page 205-219. Springer, (2009)Adaptive high-speed and ultra-low power optical interconnect for data center communications., , , , , , , and . ICTON, page 1-4. IEEE, (2017)