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Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET.

, , , , , , , , , , , and . ESSCIRC, page 183-186. IEEE, (2017)

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A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 53 (11): 3268-3279 (2018)10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders., , , , , , , , , and 3 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (10): 3529-3542 (2018)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , and 1 other author(s). ISSCC, page 408-409. IEEE, (2016)A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 55 (1): 38-48 (2020)DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology., , , , , , , , , and 1 other author(s). ESSCIRC, page 115-118. IEEE, (2017)A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET., , , , , , , , , and 6 other author(s). A-SSCC, page 239-240. IEEE, (2019)High-speed link with trellis-coded modulation and Reed-Solomon coding., , , , , and . CSCN, page 231-236. IEEE, (2016)Is There a Trade-Off Between Fairness and Accuracy? A Perspective Using Mismatched Hypothesis Testing., , , , , and . ICML, volume 119 of Proceedings of Machine Learning Research, page 2803-2813. PMLR, (2020)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)