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Disambiguation of "Loke, Alvin"

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SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration.

, , , , , , , , and . ISSCC, page 539-540. IEEE, (2021)

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Alvin Cheung

Lars Alvincz

Stephanie Alvino

Jessalyn Alvina

Kim Alving

 

Other publications of authors with the same name

Advanced IC technologies I., and . CICC, page 1. IEEE, (2012)3D ICs and 3D systems., and . CICC, IEEE, (2009)SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration., , , , , , , , and . ISSCC, page 539-540. IEEE, (2021)Session 15 - IC Technology - more Moore and more than Moore., and . CICC, IEEE, (2008)An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors., , , , , , and . IEEE J. Solid State Circuits, 47 (11): 2627-2642 (2012)Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond., , , , , , , , , and 7 other author(s). CICC, page 1-8. IEEE, (2019)A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O., , , , , , , , , and . ISSCC, page 246-247. IEEE, (2010)Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links., , , , , , , , , and 3 other author(s). CICC, page 605-608. IEEE, (2009)Introduction to the Special Issue on the IEEE 2011 Custom Integrated Circuits Conference., and . IEEE J. Solid State Circuits, 47 (8): 1798-1799 (2012)A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS., , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)