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NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element.

Z. Huang, X. Wei, G. Zgheib, W. Li, Y. Lin, Z. Jiang, K. Tu, P. Ienne, and H. Yang. FPGA, page 135-140. ACM, (2017)

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Giordano Paolo

Paolo Molteni

Paolo Bavaj

Paolo Fornara

Paolo Lobba

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Selective flexibility: Breaking the rigidity of datapath merging.M. Stojilovic, D. Novo, L. Saranovac, P. Brisk, and P. Ienne. DATE, page 1543-1548. IEEE, (2012)Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs.L. Josipovic, A. Bhattacharyya, A. Guerrieri, and P. Ienne. FPT, page 197-205. IEEE, (2019)Automatic identification of application-specific functional units with architecturally visible storage.P. Biswas, N. Dutt, P. Ienne, and L. Pozzi. DATE, page 212-217. European Design and Automation Association, Leuven, Belgium, (2006)Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor.M. Vuletic, L. Pozzi, and P. Ienne. FCCM, page 24-33. IEEE Computer Society, (2004)Designing Robust Checkers in the Presence of Massive Timing Errors.F. Worm, P. Thiran, and P. Ienne. IOLTS, page 281-286. IEEE Computer Society, (2006)Speculative Dataflow Circuits.L. Josipovic, A. Guerrieri, and P. Ienne. FPGA, page 162-171. ACM, (2019)LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only).A. Guerrieri, S. Kashani-Akhavan, M. Asiatici, P. Lombardi, B. Belhadj, and P. Ienne. FPGA, page 295. ACM, (2018)Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, A. Verma, P. Brisk, F. Gürkaynak, Y. Leblebici, and P. Ienne. FPGA, page 181-190. ACM, (2008)Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs.H. Parandeh-Afshar, and P. Ienne. FPL, page 225-231. IEEE Computer Society, (2011)Finding a Needle in the Haystack of Hardened Interconnect Patterns.S. Nikolic, G. Zgheib, and P. Ienne. FPL, page 31-37. IEEE, (2019)

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Disambiguation of "Ienne, Paolo"

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NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element.

Please choose a person to relate this publication to

Giordano Paolo

Paolo Molteni

Paolo Bavaj

Paolo Fornara

Paolo Lobba

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ienne, Paolo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element.

Please choose a person to relate this publication to

Giordano Paolo

Paolo Molteni

Paolo Bavaj

Paolo Fornara

Paolo Lobba

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element.