( en | de | ru )

 

Disambiguation of "Makris, Yiorgos"

Author of the publication

copydeleteadd this publication to your clipboard
A Hardware-Based Architecture-Neutral Framework for Real-Time IoT Workload Forensics.

, , and . IEEE Trans. Computers, 69 (11): 1668-1680 (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Phokion Makris

Georgios Makris

Jannis Makris

Makris Wassilios

Panagiotis Makris

 

Other publications of authors with the same name

Hardware-Based Real-Time Workload Forensics., , and . IEEE Des. Test, 37 (4): 52-58 (2020)On the identification of modular test requirements for low cost hierarchical test path construction., and . Integr., 40 (3): 315-325 (2007)Multiple-Bit Upset Protection in Microprocessor Memory Arrays Using Vulnerability-Based Parity Optimization and Interleaving., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (11): 2447-2460 (2015)Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain., , , , , and . Proc. IEEE, 102 (8): 1207-1228 (2014)An Experimentation Platform for On-Chip Integration of Analog Neural Networks: A Pathway to Trusted and Robust Analog/RF ICs., and . IEEE Trans. Neural Networks Learn. Syst., 26 (8): 1721-1734 (2015)Statistical Methods for Detecting Recycled Electronics: From ICs to PCBs and Beyond., , , , and . IEEE Des. Test, 41 (2): 15-22 (2024)Applying the Model-View-Controller Paradigm to Adaptive Test., and . IEEE Des. Test Comput., 29 (1): 28-35 (2012)Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (12): 2120-2133 (2017)On Improving Hotspot Detection Through Synthetic Pattern-Based Database Enhancement., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (12): 2522-2527 (2021)Nonlinear decision boundaries for testing analog circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (11): 1760-1773 (2005)