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A generic reconfigurable neural network architecture as a network on chip.

T. Theocharides, G. Link, N. Vijaykrishnan, M. Irwin, and V. Srikantam. SoCC, page 191-194. IEEE, (2004)

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P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Managing Leakage Energy in Cache Hierarchies.L. Li, I. Kadayif, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. Irwin, and A. Sivasubramaniam. J. Instruction-Level Parallelism, (2003)A clock power model to evaluate impact of architectural and technology optimizations.D. Duarte, N. Vijaykrishnan, and M. Irwin. IEEE Trans. Very Large Scale Integr. Syst., 10 (6): 844-855 (2002)Design considerations for databus charge recovery.B. Bishop, V. Lyuboslavsky, N. Vijaykrishnan, and M. Irwin. IEEE Trans. Very Large Scale Integr. Syst., 9 (1): 104-106 (2001)On the Effects of Process Variation in Network-on-Chip Architectures.C. Nicopoulos, S. Srinivasan, A. Yanamandra, D. Park, V. Narayanan, C. Das, and M. Irwin. IEEE Trans. Dependable Secur. Comput., 7 (3): 240-254 (2010)An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators.N. Gala, S. Krithivasan, W. Tsai, X. Li, V. Narayanan, and V. Kamakoti. ACM J. Emerg. Technol. Comput. Syst., 14 (1): 1:1-1:28 (2018)Process-Variation-Aware Adaptive Cache Architecture and Management.M. Mutyam, F. Wang, K. Ramakrishnan, V. Narayanan, M. Kandemir, Y. Xie, and M. Irwin. IEEE Trans. Computers, 58 (7): 865-877 (2009)A hardware accelerated multilevel visual classifier for embedded visual-assist systems.M. Cotter, S. Advani, J. Sampson, K. Irick, and V. Narayanan. ICCAD, page 96-100. IEEE, (2014)Clone Detection in Sensor Networks with Ad Hoc and Grid Topologies.R. Brooks, P. Govindaraju, M. Pirretti, N. Vijaykrishnan, and M. Kandemir. IJDSN, 5 (3): 209-223 (2009)A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.S. Srinivasa, A. Ramanathan, X. Li, W. Chen, F. Hsueh, C. Yang, C. Shen, J. Shieh, S. Gupta, M. Chang and 3 other author(s). ISLPED, page 34:1-34:6. ACM, (2018)Noise Aware Power Adaptive Partitioned Deep Networks for Mobile Visual Assist Platforms.P. Zientara, J. Sampson, and V. Narayanan. SoCC, page 186-191. IEEE, (2018)

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Disambiguation of "Vijaykrishnan, Narayanan"

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A generic reconfigurable neural network architecture as a network on chip.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Vijaykrishnan, Narayanan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A generic reconfigurable neural network architecture as a network on chip.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A generic reconfigurable neural network architecture as a network on chip.