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Versatile hardware architectures for GF(pm) arithmetic in public key cryptography.

, , and . Integr., 40 (1): 28-35 (2007)

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FPGA Implementation of a GF(2m) Tate Pairing Architecture., , , and . ARC, volume 3985 of Lecture Notes in Computer Science, page 358-369. Springer, (2006)A flexible processor for the characteristic 3 ηT pairing., , , , and . Int. J. High Perform. Syst. Archit., 1 (2): 79-88 (2007)An FPGA implementation of a GF(p) ALU for encryption processors., , , and . Microprocess. Microsystems, 28 (5-6): 253-260 (2004)A Dedicated Processor for the eta Pairing., , , , , and . IACR Cryptology ePrint Archive, (2005)Public-Key Cryptography for RFID-Tags., , , , , and . PerCom Workshops, page 217-222. IEEE Computer Society, (2007)A Reconfigurable Processor for the Cryptographic nT Pairing in Characteristic 3., , , , and . ITNG, page 11-16. IEEE Computer Society, (2007)Fast Modular Division for Application in ECC on Reconfigurable Logic., , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 786-795. Springer, (2003)An Elliptic Curve Processor Suitable For RFID-Tags., , , , , and . IACR Cryptology ePrint Archive, (2006)Hardware Implementation of the ηT Pairing in Characteristic 3., , , , and . IACR Cryptology ePrint Archive, (2006)Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve., , , , and . J. Syst. Archit., 53 (2-3): 85-98 (2007)