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ReveNAND: A Fast-Drift-Aware Resilient 3D NAND Flash Design., , , and . ACM Trans. Archit. Code Optim., 15 (2): 17:1-17:26 (2018)Secure Logic Locking with Strain-Protected Nanomagnet Logic., , , , , , , , , and 3 other author(s). DAC, page 127-132. IEEE, (2021)Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming., , , , , , , and . DATE, page 528-533. IEEE, (2019)CAPE: A cross-layer framework for accurate microprocessor power estimation., , , and . Integr., (2019)Couture: Tailoring STT-MRAM for Persistent Main Memory., , , , and . INFLOW@OSDI, USENIX Association, (2016)FuncTeller: How Well Does eFPGA Hide Functionality?, , , , , and . USENIX Security Symposium, page 5809-5826. USENIX Association, (2023)Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 171-176. ACM, (2019)Energy Efficient Power Distribution on Many-Core SoC., and . VLSID, page 488-493. IEEE, (2019)Power, Energy, and Thermal Considerations in SSD-Based I/O Acceleration., , and . HotStorage, USENIX Association, (2014)An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs., , , , and . DATE, page 1526-1531. IEEE, (2020)