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Disambiguation of "Hoskote, Yatin Vasant"

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Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking.

, , , , , , , and . FMCAD, volume 1166 of Lecture Notes in Computer Science, page 19-33. Springer, (1996)

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Vasant Desai

Vasant Shah

Vasant Kashinath Saosapurkar

 

Other publications of authors with the same name

Coverage Estimation for Symbolic Model Checking., , , and . DAC, page 300-305. ACM Press, (1999)A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 757-766 (2011)Abstraction Techniques for Validation Coverage Analysis and Test Generation., , and . IEEE Trans. Computers, 47 (1): 2-14 (1998)Abstraction of data path registers for multilevel verification of large circuits., , , and . Great Lakes Symposium on VLSI, page 11-14. IEEE, (1994)Verification of Circuits Described in VHDL through Extraction of Design Intent., , , and . VLSI Design, page 417-420. IEEE Computer Society, (1994)A Unified Framework for Design Validation and Manufacturing Test., , and . ITC, page 875-884. IEEE Computer Society, (1996)A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization., , , and . IEEE J. Solid State Circuits, 41 (10): 2314-2323 (2006)An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 43 (1): 29-41 (2008)Automated verification of temporal properties specified as state machines in VHDL., , and . Great Lakes Symposium on VLSI, page 100-105. IEEE Computer Society, (1995)Guest Editors' Introduction: Tackling Key Problems in NoCs., , and . IEEE Des. Test Comput., 25 (5): 400-401 (2008)