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Electro-thermal short pulsed simulation for SOI technology., , , , and . Microelectron. Reliab., 46 (9-11): 1482-1485 (2006)A full characterization of single pitch IO ESD protection based on silicon controlled rectifier and dynamic trigger circuit in CMOS 32 nm node., , , , , and . Microelectron. Reliab., 51 (9-11): 1614-1617 (2011)ESD protection using BIMOS transistor in 100 GHz RF application for advanced CMOS technology., , , , , , and . ICICDT, page 199-202. IEEE, (2013)On the need for a new ESD verification methodology to improve the reliability of ICs in advanced 28nm UTBB FD-SOI technology., , , , and . Microelectron. Reliab., (2016)6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology., , , , and . ICICDT, page 89-92. IEEE, (2013)BIMOS transistor and its applications in ESD protection in advanced CMOS technology., , , , , , , , and . ICICDT, page 1-4. IEEE, (2012)Impact and damage on deep sub-micron CMOS technology induced by substrate current due to ESD stress., , , , , , , and . Microelectron. Reliab., 49 (9-11): 1107-1110 (2009)Simulation, characterization and implementation of a new SCR-based device with a turn-off capability for EOS-immune ESD power supply clamps in advanced CMOS technology nodes., , , , , and . Microelectron. Reliab., (2018)Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies., , , , and . ICICDT, page 1-4. IEEE, (2017)Optimized in situ heating control on a new MOS device structure in 28nm UTBB FD-SOI CMOS technology., , and . ICICDT, page 157-160. IEEE, (2018)