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BIMOS transistor and its applications in ESD protection in advanced CMOS technology.

P. Galy, J. Jimenez, J. Bourgeat, A. Dray, G. Troussier, B. Heitz, N. Guitard, D. Marin-Cudraz, and H. Beckrich-Ros. ICICDT, page 1-4. IEEE, (2012)

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Bernd Galyga

Henri Galy

Islam Galy Khalil

Philippe Kersting

Philippe Bopp

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6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology.V. Asthana, M. Kar, J. Jimenez, S. Haendler, and P. Galy. ICICDT, page 89-92. IEEE, (2013)Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies.L. Conti, T. Bedecarrats, M. Vinet, S. Cristoloveanu, and P. Galy. ICICDT, page 1-4. IEEE, (2017)Optimized in situ heating control on a new MOS device structure in 28nm UTBB FD-SOI CMOS technology.P. Galy, R. Lethiecq, and M. Bawedin. ICICDT, page 157-160. IEEE, (2018)Computation of Self-Induced Magnetic Field Effects Including the Lorentz Force for Fast-Transient Phenomena in Integrated-Circuit Devices.W. Schoenmaker, Q. Chen, and P. Galy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (6): 893-902 (2014)BIMOS transistor and its applications in ESD protection in advanced CMOS technology.P. Galy, J. Jimenez, J. Bourgeat, A. Dray, G. Troussier, B. Heitz, N. Guitard, D. Marin-Cudraz, and H. Beckrich-Ros. ICICDT, page 1-4. IEEE, (2012)Experimental and 3D simulation correlation of a gg-nMOS transistor under high current pulse.P. Galy, V. Berland, B. Foucher, A. Guilhaume, J. Chante, S. Bardy, and F. Blanc. Microelectron. Reliab., 42 (9-11): 1299-1302 (2002)Experimental measurements and 3D simulation of the parasitic lateral bipolar transistor triggering within a single finger gg-nMOS under ESD.P. Galy, V. Berland, A. Guilhaume, F. Blanc, and J. Chante. Microelectron. Reliab., 44 (9-11): 1775-1780 (2004)Preliminary results on TFET - Gated diode in thin silicon film for IO design & ESD protection in 28nm UTBB FD-SOI CMOS technology.P. Galy, and S. Athanasiou. ICICDT, page 1-4. IEEE, (2016)Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control.V. Asthana, M. Kar, J. Jimenez, J. Noel, S. Haendler, and P. Galy. ESSCIRC, page 415-418. IEEE, (2013)Temperature and Gate Leakage Influence on the Z2-FET Memory Operation.C. Marquez, S. Navarro, C. Navarro, N. Salazar, P. Galy, S. Cristoloveanu, and F. Gámiz. ESSDERC, page 238-241. IEEE, (2019)

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Disambiguation of "Galy, Philippe"

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BIMOS transistor and its applications in ESD protection in advanced CMOS technology.

Please choose a person to relate this publication to

Bernd Galyga

Henri Galy

Islam Galy Khalil

Philippe Kersting

Philippe Bopp

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Galy, Philippe"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML BIMOS transistor and its applications in ESD protection in advanced CMOS technology.

Please choose a person to relate this publication to

Bernd Galyga

Henri Galy

Islam Galy Khalil

Philippe Kersting

Philippe Bopp

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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BIMOS transistor and its applications in ESD protection in advanced CMOS technology.