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Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.

Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch. ITC, page 488-493. IEEE Computer Society, (2003)

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Benoît Girard

Adrien Girard

Pierre Girard

Jules Girard

Yann Girard

Other publications of authors with the same name

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, J. Figueras, S. Manich, J. Teixeira, and M. Santos. ISCAS (1), page 110-113. IEEE, (1999)Logical dynamics of belief change in the community.F. Liu, J. Seligman, and P. Girard. Synthese, 191 (11): 2403-2431 (2014)Effect-cause intra-cell diagnosis at transistor level.Z. Sun, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, and E. Auvray. ISQED, page 460-467. IEEE, (2013)Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, and H. Wunderlich. VLSI-SoC, page 403-408. IEEE, (2006)Energy Model based Control for Forming Processes.P. Girard, and V. Thomson. ICINCO-ICSO, page 51-59. INSTICC Press, (2008)Prioritised ceteris paribus logic for counterfactual reasoning.P. Girard, and M. Triplett. Synthese, 195 (4): 1681-1703 (2018)DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect.J. Chen, C. Lu, J. Ni, X. Guo, P. Girard, and Y. Cheng. IEEE Trans. Very Large Scale Integr. Syst., 29 (7): 1325-1334 (2021)Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS.A. Yan, L. Wang, J. Cui, Z. Huang, T. Ni, P. Girard, and X. Wen. IEEE Trans. Very Large Scale Integr. Syst., 32 (1): 116-127 (January 2024)An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.P. Girard, O. Héron, S. Pravossoudovitch, and M. Renovell. J. Electron. Test., 22 (2): 161-172 (2006)Delay-Fault Diagnosis by Critical-Path Tracing.P. Girard, C. Landrault, and S. Pravossoudovitch. IEEE Des. Test Comput., 9 (4): 27-32 (1992)

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Disambiguation of "Girard, Patrick"

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Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.

Please choose a person to relate this publication to

Benoît Girard

Adrien Girard

Pierre Girard

Jules Girard

Yann Girard

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Girard, Patrick"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.

Please choose a person to relate this publication to

Benoît Girard

Adrien Girard

Pierre Girard

Jules Girard

Yann Girard

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.