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Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations.

, , , , and . ICCAD, page 382-388. IEEE, (2014)

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The Titanic: what went wrong!, , , , , and . DAC, page 349-350. ACM, (2005)Design-aware lithography., , and . ISPD, page 3-8. ACM, (2012)An efficient surface-based low-power buffer insertion algorithm., , , , and . ISPD, page 86-93. ACM, (2005)Opportunities in power distribution network system optimization: from EDA perspective., and . ISPD, page 149-150. ACM, (2014)Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events., , and . DAC, page 69-72. ACM, (2006)Characterizing Process Variation in Nanometer CMOS., and . DAC, page 396-399. IEEE, (2007)Analyzing the impact of process variations on parametric measurements: Novel models and applications., and . DATE, page 375-380. IEEE, (2009)A 32nm 0.5V-supply dual-read 6T SRAM., , , , , , , , , and 5 other author(s). CICC, page 1-4. IEEE, (2010)Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations., , , , and . ICCAD, page 382-388. IEEE, (2014)When bad things happen to good chips (panel session)., , , , , , , and . DAC, page 736-737. ACM, (2000)