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Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits., , и . ISCAS, стр. 3150-3153. IEEE, (2009)A general model for differential power analysis attacks to static logic circuits., , и . ISCAS, стр. 3346-3349. IEEE, (2008)A gate-level strategy to design Carry Select Adders., , и . ISCAS (2), стр. 465-468. IEEE, (2004)26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltage., , и . ISSCC, стр. 440-441. IEEE, (2017)EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm2 area in 40nm CMOS., , и . A-SSCC, стр. 241-244. IEEE, (2017)17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI., , , , , и . ISSCC, стр. 310-312. IEEE, (2016)A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing., , и . ISSCC, стр. 44-46. IEEE, (2018)Power-delay optimization of D-latch/MUX source coupled logic gates., и . I. J. Circuit Theory and Applications, 33 (1): 65-86 (2005)Modelling of source-coupled logic gates., , и . I. J. Circuit Theory and Applications, 30 (4): 459-477 (2002)Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore's Law., , и . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (4): 653-678 (2018)