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Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits.

, , , , and . ISVLSI, page 362-367. IEEE Computer Society, (2015)

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Analyzing testability from behavioral to RT level., , and . ED&TC, page 158-165. IEEE Computer Society, (1997)High-level synthesis for easy testability., , and . ED&TC, page 198-206. IEEE Computer Society, (1995)New testing procedure for finding insertion sites of stealthy hardware trojans., , , , and . DATE, page 776-781. ACM, (2015)A Flip-Flop Matching Engine to Verify Sequential Optimizations., , and . Comput. Artif. Intell., 23 (5): 437-460 (2004)Scan chain encryption for the test, diagnosis and debug of secure circuits., , , , , and . ETS, page 1-6. IEEE, (2017)Laser attacks on integrated circuits: From CMOS to FD-SOI., , , , , , , , , and . DTIS, page 1-6. IEEE, (2014)A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans., , , , and . IOLTS, page 49-54. IEEE, (2014)Compression-based SoC Test Infrastructures., , and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-15. Springer, (2007)On Preventing SAT Attack with Decoy Key-Inputs., , , and . ISVLSI, page 114-119. IEEE, (2021)An Integrated Validation Environment for Differential Power Analysis., , and . DELTA, page 527-532. IEEE Computer Society, (2008)