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Towards the next generation of low-power test technologies.. ASICON, page 232-235. IEEE, (2011)Design of Low-Cost Approximate CMOS Full Adders., , , , , , and . ISCAS, page 1-5. IEEE, (2023)SASL-JTAG: A Light-Weight Dependable JTAG., , , , , , , , and . DFT, page 1-3. IEEE, (2023)Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing., , , and . ITC, page 1-10. IEEE Computer Society, (2008)Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard., , , , , , , , , and 6 other author(s). ITC, page 1-9. IEEE Computer Society, (2008)Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing., , and . ITC, page 1-7. IEEE Computer Society, (2011)Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications., , , , , , and . Microelectron. J., (September 2023)A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets., , , , , , and . ATS, page 1-5. IEEE, (2020)A High-Performance and P-Type FeFET-Based Non-Volatile Latch., , , , and . ATS, page 1-5. IEEE, (2023)Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test., , and . PRDC, page 124-129. IEEE, (2019)