( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs.

, , , , , , , , , и . ICCD, стр. 255-263. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

sushil

Sushil Kumar

Sushil Kumar

Sushil Kumar Verma

Sushil Kumar Tiwary

 

Другие публикации лиц с тем же именем

Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems., , , , , , , , , и . ISCAS, стр. 1-4. IEEE, (2017)SRAM designs for 5nm node and beyond: Opportunities and challenges., , , , , и . ICICDT, стр. 1-4. IEEE, (2017)Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications., , , , , , , , , и 2 other автор(ы). DAC, стр. 13. ACM, (2019)Design Technology co-optimization for N10., , , , , , , , , и 18 other автор(ы). CICC, стр. 1-8. IEEE, (2014)A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs., , , , , , , , , и . ICCD, стр. 255-263. IEEE, (2019)Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks., , , , , , , , , и 3 other автор(ы). DATE, стр. 103-108. IEEE, (2018)Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM., , , , , , , и . ICICDT, стр. 1-4. IEEE, (2015)