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Disambiguation of "Pérez, José Ignacio Gómez"

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A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs.

, , , , , , , , , and . ICCD, page 255-263. IEEE, (2019)

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José Gómez

Ignacio Pérez Domínguez

Ignacio Dolado Pérez

Ignacio Figueroa Pérez

María José Carrascosa Gómez

 

Other publications of authors with the same name

Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices., , , , , and . ACM Trans. Embed. Comput. Syst., 21 (1): 3:1-3:20 (2022)Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM., , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (12): 5327-5332 (2022)Improving the Representativeness of Simulation Intervals for the Cache Memory System., , , , and . CoRR, (2024)RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education., , , , , , , and . FPL, page 145-150. IEEE, (2021)Design exploration of a NVM based hybrid instruction memory organization for embedded platforms., , , , , , and . Des. Autom. Embed. Syst., 17 (3-4): 459-483 (2013)COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications., , , and . J. Syst. Archit., (December 2023)A power measurement environment for PCIe accelerators., , , , and . Comput. Sci. Res. Dev., 30 (2): 115-124 (2015)Spatio-Temporal Resolution of Irradiance Samples in Machine Learning Approaches for Irradiance Forecasting., , , , , , and . IEEE Access, (2020)System level exploration of a STT-MRAM based level 1 data-cache., , , , and . DATE, page 1311-1316. ACM, (2015)A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs., , , , , , , , , and . ICCD, page 255-263. IEEE, (2019)