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Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems., , , , , , , , , and . ISCAS, page 1-4. IEEE, (2017)SRAM designs for 5nm node and beyond: Opportunities and challenges., , , , , and . ICICDT, page 1-4. IEEE, (2017)Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications., , , , , , , , , and 2 other author(s). DAC, page 13. ACM, (2019)Design Technology co-optimization for N10., , , , , , , , , and 18 other author(s). CICC, page 1-8. IEEE, (2014)A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs., , , , , , , , , and . ICCD, page 255-263. IEEE, (2019)Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks., , , , , , , , , and 3 other author(s). DATE, page 103-108. IEEE, (2018)Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)