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Time Management for Low-Power Design of Digital Systems., , , , , , and . J. Low Power Electron., 4 (3): 410-419 (2008)RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems., , , and . J. Electron. Test., 17 (3-4): 311-319 (2001)Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip., , , , , and . J. Electron. Test., 21 (4): 349-363 (2005)Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing., , , , , , , , and . J. Low Power Electron., 7 (2): 185-198 (2011)On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications., , , , and . J. Low Power Electron., 7 (4): 562-572 (2011)Signal Integrity Enhancement in Digital Circuits., , , , , , , and . IEEE Des. Test Comput., 25 (5): 452-461 (2008)Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage., , , , , and . DDECS, page 279-284. IEEE Computer Society, (2006)On-Detector Electronics of the Clear PEM Scanner., , , , , , , , , and 15 other author(s). BIODEVICES, page 355-358. INSTICC Press, (2009)Data Acquisition Electronics for PET Mammography Imaging., , , , , , , , , and 5 other author(s). BIODEVICES, page 192-197. INSTICC Press, (2009)RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST., , , , , and . ITC, page 814-823. IEEE Computer Society, (2002)