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MERIT: Tensor Transform for Memory-Efficient Vision Processing on Parallel Architectures.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (3): 791-804 (2020)

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Subword Parallel Architecture for Connected Component Labeling and Morphological Operations., and . APCCAS, page 936-939. IEEE, (2006)Distributed video codec with spatiotemporal side information., , , , and . ISCAS, page 1-4. IEEE, (2017)Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements., , and . IEEE Trans. Circuits Syst. Video Techn., 15 (9): 1156-1169 (2005)Enhanced temporal error concealment algorithm with edge-sensitive processing order., , , and . ISCAS, page 3466-3469. IEEE, (2008)A hardware accelerator for video segmentation using programmable morphology PE array., , and . ISCAS (4), page 341-344. IEEE, (2002)Fast disparity estimation algorithm for mesh-based stereo image/video compression with two-stage hybrid approach., , , , and . VCIP, volume 5150 of Proceedings of SPIE, page 1521-1530. SPIE, (2003)Occlusion-aware Video Temporal Consistency., , and . ACM Multimedia, page 777-785. ACM, (2017)Perceptual Quality-Regulable Video Coding System With Region-Based Rate Control Scheme., , , and . IEEE Trans. Image Processing, 22 (6): 2247-2258 (2013)Back-Projection Lightweight Network for Accurate Image Super Resolution., and . ACCV (5), volume 11365 of Lecture Notes in Computer Science, page 135-151. Springer, (2018)Convolutional Neural Network Accelerator with Vector Quantization., , , and . ISCAS, page 1-5. IEEE, (2019)