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Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract).

, , , and . ASP-DAC/VLSI Design, page 16-17. IEEE Computer Society, (2002)

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Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers., , and . ISCAS, page 2854-2857. IEEE, (2007)A wideband IM3 cancellation technique for CMOS attenuators., , , , and . ISSCC, page 78-80. IEEE, (2012)Hardware Implementations for Voice Activity Detection: Trends, Challenges and Outlook., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (3): 1083-1096 (March 2023)Effects of packaging and process spread on a mobility-based frequency reference in 0.16-μm CMOS., , , , , and . ESSCIRC, page 511-514. IEEE, (2011)Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking., , , and . CICC, page 1-4. IEEE, (2017)Reconfigurable SDR front-end techniques.. CICC, page 1-103. IEEE, (2014)5.5 A forward-body-bias tuned 450MHz Gm-C 3rd-order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply., , , , , and . ISSCC, page 1-3. IEEE, (2015)A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time., , , , and . ISSCC, page 314-605. IEEE, (2007)A multi-step P-cell for LNA design automation., , and . ISCAS, page 2550-2553. IEEE, (2008)On the Suitability of Discrete-Time Receivers for Software-Defined Radio., , and . ISCAS, page 2522-2525. IEEE, (2007)