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Disambiguation of "Parulkar, Ishwar"

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Allocation Techniques for Reducing BIST Area Overhead of Data Paths.

, , and . J. Electron. Test., 13 (2): 149-166 (1998)

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Ishwar Singh Dagar

Ishwar Nath Topa

 

Other publications of authors with the same name

Panel: Reliability of data centers: Hardware vs. software., , , , , and . DATE, page 1620. IEEE Computer Society, (2010)Introducing redundant computations in RTL data paths for reducing BIST resources., , and . ACM Trans. Design Autom. Electr. Syst., 6 (3): 423-445 (2001)Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 44 (1): 7-17 (2009)A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors., , , , and . ITC, page 726-735. IEEE Computer Society, (2002)DFX of a 3rd Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2008)Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and Systems., and . IOLTS, page 74-77. IEEE Computer Society, (2005)Scheduling and Module Assignment for Reducing Bist Resources., , and . DATE, page 66-73. IEEE Computer Society, (1998)Comprehensive Approach to High-Performance Server Chipset Debug., and . IEEE Des. Test Comput., 26 (3): 70-77 (2009)Allocation Techniques for Reducing BIST Area Overhead of Data Paths., , and . J. Electron. Test., 13 (2): 149-166 (1998)Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in field., , , and . ITC, page 9. IEEE Computer Society, (2005)