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Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology.

G. Beanato, P. Giovannini, A. Cevrero, P. Athanasopoulos, M. Zervas, Y. Temiz, and Y. Leblebici. IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (2): 295-306 (2012)

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Athanasios Athanasopoulos

Apostolos Athanasopoulos

Ioannis Athanasopoulos

Panagiotis Vougioukas

Panagiotis Triantafillou

Other publications of authors with the same name

Using 3D integration technology to realize multi-context FPGAs.A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, M. Skerlj, P. Brisk, Y. Leblebici, and P. Ienne. FPL, page 507-510. IEEE, (2009)3D configuration caching for 2D FPGAs.A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, P. Brisk, Y. Leblebici, P. Ienne, and M. Skerlj. FPGA, page 286. ACM, (2009)Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, A. Verma, S. Attarzadeh-Niaki, C. Nicopoulos, F. Gürkaynak, P. Brisk, Y. Leblebici, and P. Ienne. ACM Trans. Reconfigurable Technol. Syst., 2 (2): 13:1-13:36 (2009)Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology.G. Beanato, P. Giovannini, A. Cevrero, P. Athanasopoulos, M. Zervas, Y. Temiz, and Y. Leblebici. IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (2): 295-306 (2012)3D-MMC: a modular 3D multi-core architecture with efficient resource pooling.T. Zhang, A. Cevrero, G. Beanato, P. Athanasopoulos, A. Coskun, and Y. Leblebici. DATE, page 1241-1246. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A flexible DSP block to enhance FPGA arithmetic performance.H. Parandeh-Afshar, A. Cevrero, P. Athanasopoulos, P. Brisk, Y. Leblebici, and P. Ienne. FPT, page 70-77. IEEE Computer Society, (2009)Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs.F. Sun, A. Cevrero, P. Athanasopoulos, and Y. Leblebici. VLSI-SoC, page 149-154. IEEE, (2010)Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, A. Verma, P. Brisk, F. Gürkaynak, Y. Leblebici, and P. Ienne. FPGA, page 181-190. ACM, (2008)Memory organization and data layout for instruction set extensions with architecturally visible storage.P. Athanasopoulos, P. Brisk, Y. Leblebici, and P. Ienne. ICCAD, page 689-696. ACM, (2009)

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Disambiguation of "Athanasopoulos, Panagiotis"

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Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology.

Please choose a person to relate this publication to

Athanasios Athanasopoulos

Apostolos Athanasopoulos

Ioannis Athanasopoulos

Panagiotis Vougioukas

Panagiotis Triantafillou

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Athanasopoulos, Panagiotis"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology.

Please choose a person to relate this publication to

Athanasios Athanasopoulos

Apostolos Athanasopoulos

Ioannis Athanasopoulos

Panagiotis Vougioukas

Panagiotis Triantafillou

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology.