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An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees.

H. An, Y. Chen, Z. Fan, Q. Zhang, P. Abillama, H. Kim, D. Blaauw, and D. Sylvester. ISSCC, page 422-423. IEEE, (2023)

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An You

An Mengi

An Luo

Yang An

Other publications of authors with the same name

An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks.H. An, S. Schiferl, S. Venkatesan, T. Wesley, Q. Zhang, J. Wang, K. Choo, S. Liu, B. Liu, Z. Li and 6 other author(s). IEEE J. Solid State Circuits, 56 (4): 1071-1081 (2021)A Reconfigurable Analog FIR Filter Achieving -70dB Rejection with Sharp Transition for Narrowband Receivers.C. Tseng, Z. Feng, Z. Fan, H. An, Y. Wang, H. Kim, and D. Blaauw. VLSI Technology and Circuits, page 1-2. IEEE, (2023)SONA: An Accelerator for Transform-Domain Neural Networks with Sparse-Orthogonal Weights.P. Abillama, Z. Fan, Y. Chen, H. An, Q. Zhang, S. Choi, D. Blaauw, D. Sylvester, and H. Kim. ASAP, page 18-26. IEEE, (2023)14.1-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC.K. Choo, H. An, D. Sylvester, and D. Blaauw. ISSCC, page 372-374. IEEE, (2021)A 22nm 3.5TOPS/W Flexible Micro-Robotic Vision SoC with 2MB eMRAM for Fully-on-Chip Intelligence.Q. Zhang, H. An, Z. Fan, Z. Wang, Z. Li, G. Wang, H. Kim, D. Blaauw, and D. Sylvester. VLSI Technology and Circuits, page 72-73. IEEE, (2022)A Power-Efficient Brain-Machine Interface System With a Sub-mw Feature Extraction and Decoding ASIC Demonstrated in Nonhuman Primates.H. An, S. Nason-Tomaszewski, J. Lim, K. Kwon, M. Willsey, P. Patil, H. Kim, D. Sylvester, C. Chestek, and D. Blaauw. IEEE Trans. Biomed. Circuits Syst., 16 (3): 395-408 (2022)1.03pW/b Ultra-Low Leakage Voltage-Stacked SRAM for Intelligent Edge Processors.J. Wang, H. An, Q. Zhang, H. Kim, D. Blaauw, and D. Sylvester. VLSI Circuits, page 1-2. IEEE, (2020)A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge.H. An, S. Venkatesan, S. Schiferl, T. Wesley, Q. Zhang, J. Wang, K. Choo, S. Liu, B. Liu, Z. Li and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Audio and Image Cross-Modal Intelligence via a 10TOPS/W 22nm SoC with Back-Propagation and Dynamic Power Gating.Z. Fan, H. An, Q. Zhang, B. Xu, L. Xu, C. Tseng, Y. Peng, A. Cao, B. Liu, C. Lee and 7 other author(s). VLSI Technology and Circuits, page 18-19. IEEE, (2022)An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees.H. An, Y. Chen, Z. Fan, Q. Zhang, P. Abillama, H. Kim, D. Blaauw, and D. Sylvester. ISSCC, page 422-423. IEEE, (2023)

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Disambiguation of "An, Hyochan"

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An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees.

Please choose a person to relate this publication to

An You

An Mengi

An Luo

An Luo

Yang An

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "An, Hyochan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees.

Please choose a person to relate this publication to

An You

An Mengi

An Luo

An Luo

Yang An

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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Chicago
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An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees.