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A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 52 (7): 1863-1875 (2017)A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI., , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)Reply to discussion by B. Keller and R. Nance., and . Journal of Software Maintenance, 7 (5): 379-380 (1995)HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression., , , , , and . CoRR, (2022)Verifying High-Level Latency-Insensitive Designs with Formal Model Checking., , , , , , and . CoRR, (2021)Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk)., , , and . ICCAD, page 70:1-70:4. IEEE, (2020)MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification., , , , , and . DATE, page 1825-1828. IEEE, (2021)The Atacama Cosmology Telescope: High-resolution component-separated maps across one-third of the sky, , , , , , , , , and 144 other author(s). (2023)cite arxiv:2307.01258Comment: The Compton-y map and associated products will be made publicly available upon publication of the paper. The CMB T and E mode maps will be made available when the DR6 maps are made public.Simba: scaling deep-learning inference with chiplet-based architecture., , , , , , , , , and 7 other author(s). Commun. ACM, 64 (6): 107-116 (2021)Energy-Efficient System Design Through Adaptive Voltage Scaling.. University of California, Berkeley, USA, (2017)