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A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (1): 16-20 (2010)A power-efficient capacitor structure for high-speed charge recycling SAR ADCs., , , , , and . ICECS, page 642-645. IEEE, (2008)A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier., , , , and . ISCAS, page 5-8. IEEE, (2008)Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs., , , , , and . VLSI Design, (2010)Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (8): 607-611 (2010)A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS., , , , , , and . ESSCIRC, page 377-380. IEEE, (2012)A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications., , , , and . IEEE Access, (2020)A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration., , , , and . IEEE J. Solid State Circuits, 55 (3): 693-705 (2020)An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H., , , , , , , , and . ESSCIRC, page 218-221. IEEE, (2010)A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing., , , , and . VLSI Circuits, page 76-. IEEE, (2019)