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Disambiguation of "U, Seng-Pan"

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An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H.

, , , , , , , , and . ESSCIRC, page 218-221. IEEE, (2010)

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Katja Seng

Peter Seng

Stefan Seng

Helmut Seng

Gerhard Seng

 

Other publications of authors with the same name

Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems., , and . ISCAS (4), page 441-444. IEEE, (2002)A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-sampling., , , , , and . ISCAS (1), page 1061-1064. IEEE, (2003)A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration., , , , and . IEEE J. Solid State Circuits, 53 (3): 850-860 (2018)60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration., , , , , , , and . IEEE J. Solid State Circuits, 52 (10): 2576-2588 (2017)An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC., , , , , , and . IEEE J. Solid State Circuits, 47 (11): 2763-2772 (2012)A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC., , , , and . IEEE J. Solid State Circuits, 51 (2): 365-377 (2016)A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μ hboxm CMOS., , and . IEEE J. Solid State Circuits, 39 (1): 87-99 (2004)Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_cm$ -Based Switching., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 1168-1172 (2017)Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (7): 2603-2607 (2016)A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS., , , , and . A-SSCC, page 285-288. IEEE, (2017)