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Combining Two Local Search Approaches to Hypergraph Partitioning.

, and . IJCAI, page 1546-. Morgan Kaufmann, (2003)

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Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (12): 2107-2119 (2008)Optimal partitioners and end-case placers for standard-cell layout., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (11): 1304-1313 (2000)Synthesis of reversible logic circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (6): 710-722 (2003)On wirelength estimations for row-based placement., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (9): 1265-1278 (1999)Resolution cannot polynomially simulate compressed-BFS., , and . Ann. Math. Artif. Intell., 44 (1-2): 121-156 (2005)Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting., , , and . DAC, page 349-354. ACM Press, (1999)Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability., , and . Modern Circuit Placement, Springer, (2007)On wirelength estimations for row-based placement., , , , and . ISPD, page 4-11. ACM, (1998)Faster minimization of linear wirelength for global placement., , , , , , and . ISPD, page 4-11. ACM, (1997)Benchmarking for large-scale placement and beyond., , , , , and . ISPD, page 95-103. ACM, (2003)