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Access to streams in multiprocessor systems., , and . PDP, page 310-316. IEEE, (1993)Breaking the bandwidth wall in chip multiprocessors., , , and . ICSAMOS, page 255-262. IEEE, (2011)Speculative early register release., , , and . Conf. Computing Frontiers, page 291-302. ACM, (2006)Novel SRAM bias control circuits for a low power L1 data cache., , , , and . NORCHIP, page 1-6. IEEE, (2012)Picos: A hardware runtime architecture support for OmpSs., , , , and . Future Gener. Comput. Syst., (2015)Dynamic Tolerance Region Computing for Multimedia., , and . IEEE Trans. Computers, 61 (5): 650-665 (2012)A performance evaluation of the multiple bus network for multiprocessor systems., , , , and . SIGMETRICS, page 200-206. ACM, (1983)Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Runtime-assisted cache coherence deactivation in task parallel programs., , , , and . SC, page 35:1-35:12. IEEE / ACM, (2018)Parallel Computer Architecture., , , and . Euro-Par, volume 1900 of Lecture Notes in Computer Science, page 537-538. Springer, (2000)