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A Fast and Accurate Middle End of Line Parasitic Capacitance Extraction for MOSFET and FinFET Technologies Using Machine Learning.

, , and . ASP-DAC, page 371-376. IEEE, (2022)

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Accuracy-Based Hybrid Parasitic Capacitance Extraction Using Rule-Based, Neural-Networks, and Field-Solver Methods., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (12): 5681-5694 (2022)RC Parasitic-Aware Layout Analysis and Routing Optimization Methodology., , and . IEEE Access, (2022)Fast and Accurate Machine Learning Compact Models for Interconnect Parasitic Capacitances Considering Systematic Process Variations., , and . IEEE Access, (2022)Chameleon ART: a non-optimization based analog design migration framework., , , , , , , and . DAC, page 885-888. ACM, (2006)Analog IP migration using design knowledge extraction., , , and . CICC, page 333-336. IEEE, (2004)Connectivity-Based Machine Learning Compact Models for Interconnect Parasitic Capacitances., , and . MLCAD, page 1-6. IEEE, (2021)A Fully Automated Approach for Analog Circuit Reuse., , , and . IWSOC, page 237-240. IEEE Computer Society, (2004)A simple model for on-chip microstrip transmission lines in millimeter wave circuits., , , , , and . ICM, page 121-124. IEEE, (2016)A Fast and Accurate Middle End of Line Parasitic Capacitance Extraction for MOSFET and FinFET Technologies Using Machine Learning., , and . ASP-DAC, page 371-376. IEEE, (2022)A 1.5 V opamp design with high gain wide bandwidth and its application in a high Q bandpass filter operating at 10.7 MHz., , and . ICECS, page 185-188. IEEE, (2002)