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EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory., , , , , и . IEEE Trans. Computers, 67 (1): 32-44 (2018)A Study of Data Layout in Multi-channel Processing-In-Memory Architecture., , , и . ICSCA, стр. 134-138. ACM, (2018)Asymmetric Slew Logic Threshold Method on Near Threshold Region., , , и . ICSCA, стр. 317-321. ACM, (2018)Automatic source code specialization for energy reduction., , и . ISLPED, стр. 80-83. ACM, (2001)An Energy and Performance Efficient DVFS Scheme for Irregular Parallel Divide-and-Conquer Algorithms on the Intel SCC., , , и . IEEE Comput. Archit. Lett., 13 (1): 13-16 (2014)GPU-based acceleration of an RNA tertiary structure prediction algorithm., , , , и . Comput. Biol. Medicine, 43 (8): 1011-1022 (2013)High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event Evaluation., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (8): 1274-1278 (2009)Multitoken-Based Power Management for NAND Flash Storage Devices., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2898-2910 (2020)Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory., и . IEEE Trans. Very Large Scale Integr. Syst., 16 (3): 289-301 (2008)Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis., , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (4): 875-878 (2007)